1. Field of The Invention
This invention relates to an SOIMOS transistor device of the type wherein the source resistance is low and the drain breakdown voltage is high.
2. Description Of The Prior Art
Known (LDD)MOS transistor devices are those as shown in section in FIGS. 1 to 3 wherein FIG. 1 is a sectional view of an LDD-type MOS transistor. In recent years, in order to increase a drain breakdown voltage, many attempts have been made to fabrication of MOD transistor devices which have an LDD structure. FIG. 1 shows a MOS transistor device of the LDD structure. In the figure, indicated at 1 is a p-type semiconductor substrate, at 2 is an n.sup.+ -type source, at 3 is an n.sup.+ -type drain, at 4 is an n.sup.- -type lightly doped source region, at 5 is an n.sup.- -type lightly doped drain region, at 6 is a gate insulating film, at 7 is a gate electrode and at 8 is side walls formed on the side walls of the gate electrode 7.
This type of SOIMOS transistor device is formed, prior to formation of the side walls 8, by implanting impurity ions through the mask of the gate electrode 7 to form the lightly doped source region 4 and the lightly doped drain region 5. Then, the side walls 8 are formed, followed by ion implantation of an impurity through the mask of the gate electrode 7 and the side walls 8 to form the source 2 and the drain 3. The formation of the lightly doped region 5 permits impact ionization to be reduced which will take place at the end side of the drain of the channel, eventually leading to an increase of the drain breakdown voltage.
However, the MOS transistor has the problem that the parasitic resistance at the side of the source becomes great with a lowering of gm. This is because the MOS transistor device having the LDD structure is so arranged that the lightly doped regions 4,5 are turned away from the lower side toward the outside of the gate electrode 7 or toward the sides of the source 2 and the drain 3.
In order to increase the breakdown voltage of the drain without increasing the source resistance, attempts have been made to position the lightly doped regions 4,5 below the gate electrode 7.
FIGS. 2 and 3 are, respectively, sectional views of the devices made by such attempts.
FIG. 2 shows a MOS transistor device wherein a gate electrode 17a is made thin at the end portions of the source and drain sides. An impurity is subjected to ion implantation through the mask of the gate electrode 17a to form a source 12 and a drain 13 having lightly doped regions 14, 15 beneath the thin end portions at the source and drain sides.
The MOS transistor device of FIG. 3 has a lightly doped region with a low surface impurity concentration below a gate electrode 27, as indicated by the broken line, by ion implantation in an oblique direction through thermal treatment.
However, the MOS transistor of FIG. 2 has the problem that the gate electrode 17a has to be formed as having partially different thicknesses, involving a complicated procedure. The MOS transistor device of FIG. 3 has also the problem that it is difficult to properly control the concentration distributions of a source 22 and a drain 23 as desired, i.e. the process control is difficult, with relatively poor reproducibility and, thus, it is difficult to reproduce desired characteristics.